Wiring substrates that are used to mount electronic components such as semiconductor chips have various shapes and various structures. Semiconductor chips have become highly integrated and highly sophisticated. This has increased the demand for finer wirings formed in a wiring substrate on which a semiconductor chip is mounted. In a prior art wiring substrate, to form finer wiring, a wiring pattern and an insulation layer are formed on a base substrate, and columnar connection terminals are located on the wiring pattern that is exposed from the insulation layer. Japanese Laid-Open Patent Publication Nos. 2014-225632 and 2010-129996 each describe the structure of such a wiring substrate.
In the above wiring substrate, the insulation layer and the connection terminals have different thermal expansion coefficients. Thus, when a reliability test is performed on the wiring substrate through a heating cycle, thermal stress is generated by the difference in thermal expansion coefficient between the insulation layer and the connection terminals. The thermal stress concentrates on the interface between the insulation layer and each connection terminal. Thus, cracks or the like are easily formed at the interface between the insulation layer and the connection terminal.